Common Source (FET) Amplifier

One of the three base amplifier circuits with FET (or JFET) transistor is the circuit with common source. In this circuit, the common electrode is the source of the FET transistor, the input signal leads on the gate and the output signal is taken from the drain. The common source circuit is shown on Picture 1. This is the simplest circuit configuration only with base elements for proper polarization of the transistor and with input signal generator and output load for simple analysis of the circuit.Again, we will not use here a deep math analysis of the circuit and it's elements, since the LT spice is doing that for us. However, our goal here is to analyze the basic principles of this circuit, and to see how the basic parameters affect the circuit response.

First, let's see which are the basic elements for the proper work of this circuit. The power supply Vdd is the DC voltage source. Vdd provides static mode of work of this circuit.
Here, the transistor J1 is a N-channel JFET transistor. The resistor Rd is drain's resistor and the resistor Rs is source's resistor. Here, the electrolytic capacitor Cs has important role, since with this capacitor and through the resistor Rg we got proper polarization of the gate of the FET transistor. Now comes the Ac mode. We have AC input voltage signal Vi which should be amplified passing through this circuit as output voltage signal Vo. Just to be clear, Vi and Vo are voltages, however, we can consider the input signal as current Ii, then the output will be considered as output current signal Io. The AC signals are passing through the coupling capacitors C1 and C2. The input signal is provided by the sinusoidal voltage source, and it leads to the gate of the J1 through the C1. The amplified output signal is taken from the drain of the J1, and it leads to the load Rl through the C2.

Picture 1: Common Source (FET) Amplifier Circuit



Time-domain analysis

First, the transient analysis simulation is done. The transient analysis of the circuit was performed as non-linear time-domain simulation. The time domain wave forms of the voltage signals of input and output are shown on the Picture 2. The green color trace is the input voltage measured right before C1 (actually, that's the Vi waveform) and the blue color trace is the output voltage measured right after the C2 (actually, that's the Vo wave form - the voltage of the load Rl). As we can see from the Picture 2, the output signal is relatively ok, there are not any visible distortions of its wave form. The amplitude of the output signal is about 1.3 V, which means that with this circuit configuration we achieved a voltage amplification of Av = - 13. So, these are the visible results from the plot. Now, we can see more precise results from the simulation through the numbers measured in LT Spice (approximate values):

For Vi max = + 100 mV => Vo min = - 1.348 V;
For Vi min = - 100 mV => Vo max = + 1.308 mV;

--> Av = - 13 (approximate voltage amplification Av = Vo/Vi)

For Ic1 min = - 100 nA => IRl max = + 134.8 uA;
For IC1 max = + 100 nA => IRl min = - 131.5 uA;

--> Ai = - 1300 (approximate current amplification Ai = Io/Ii)

Picture 2: Transient analysis - input and output voltage wave forms (time-domain)


The minimum value of the Vo measured is bigger than maximum for about 40 mV, which for a 0.1V amplitude of sinusoidal signal is about 2.9 % distortion. This means that when positive half period is present in the output signal, The transistor reach its limit of the normal active region a little bit faster than when negative half-period is present, and it can't reach the same max value as for negative half-period, but the difference is small, so we can say that the static mode of operation of this circuit is relatively well adjusted (for AC small signals with amplitudes up to 100 mV). Also, from the values that we got from the simulation results for this common source circuit configuration the calculated values for amplification are about Av = - 13 (for voltage) and Ai = - 1300 (for current). As we can notice, the current amplification of this circuit is big, which was expected since the input current (into the gate electrode of the FET) is too low, approximately near zero.



Frequency-domain analysis

The phase-frequency characteristics of this common emitter circuit were measured with AC analysis in LT spice. LT Spice computes the small signal AC behavior of the circuit linearized about its DC operating point. In this AC simulation were used these parameters:

Type of Sweep: Octave;
Number of points per octave: 1;
Start Frequency: 20 Hz;
Stop Frequency: 10 MHz;

Picture 3: AC Analysis - output voltage [dB] and its phase [degrees] (frequency-domain)


The simulation results are shown on Picture 3. The solid green line on the graph represents the Vo[dB] and the dashed green line represents the phase of the Vo, both in frequency-domain. The maximum of the Vo is the 22.6 dB which is achieved for the frequencies around 10 kHz and phase in that cases is -180 degrees. Vo decreases for 3 dB (falls on 19.6 dB) at frequency of 144 Hz with phase of -130 degrees and group delay of 724 us, that's low frequency, and the high frequency is at 650 kHz with phase of -225 degrees and group delay of 134 ns. At frequency of 20 Hz, the magnitude of the output voltage Vo is 4.2 dB with phase of -66 degrees and group delay of 3.6 ms.

So, according to the results of the AC analysis of this circuit, the low frequency limit is fl = 144 Hz, and the high frequency limit is fh = 650 kHz.

The reduction of the amplification at low frequencies is caused by the coupling capacitors C1 and C2, while the reduction at high frequencies is caused by the parasitic capacitances of the transistor and the parallel capacitances which reconnect the signal to the ground.